Can I detect from which mode (EL1, EL0,...) SError interrupt was caused?

Dear all, As I know there are separate vectors to handle SError caused by EL0 and EL1. My queston is follow: Due to fact that SError is asynchronous, can I rely on fact that if cpu entered serror_el1_vector...
How can I trigger an SError exception on a cortex A processor

Is there a reproducible way of intentionnaly triggering a SError on a cortex A implementation (CortexA53 for example), I need this to implement handlers for different errors and I need this to test my...
How can I trigger an SError exception on a cortex A processor

Is there a reproducible way of intentionnaly triggering a SError on a cortex A implementation (CortexA53 for example), I need this to implement handlers for different errors and I need this to test my...
SError interrupt due to LDAXRB instruction when disable cache on NXP ls1046a

Hi Experts My code runs in EL3 on ls1046a RDB in bare mental environment. Here are the focus code after start up. Step 1: Disable data cache, the the sctlr_el3 is changed from 0x00c5183d to 0x00c51839...
Can I detect from which mode (EL1, EL0,...) SError interrupt was caused?

Dear all, As I know there are separate vectors to handle SError caused by EL0 and EL1. My queston is follow: Due to fact that SError is asynchronous, can I rely on fact that if cpu entered serror_el1_vector...