DRAM address mapping on a Cortex-A72 ARMv8

HI Everyone, I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ? is there...
DRAM address mapping on a Cortex-A72 ARMv8

HI Everyone, I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ? is there...
How could I read cache internal memory in Cortex-A72

Hi, I could find the register for direct accessing to internal memory of cache in Cortex-a53. Could I do it in CA72? Thanks.
Linux/C/mmap(): Avoiding the flushing of memory mapped region created using mmap to the underlying file

Hello, I am using mmap() to map device file "mtdblock0" into virtual address space of one process1. Some data whose value changes continuously for some time are stored in memory mapped region...
[armv8][cortex-a72] why must flush data cache when I tried to map a SRAM area?

I tried to map a SRAM area, I add that area (from 0x700000000 to 0x70FFFFFF) to page table and set Memory Attribute Indirection Register as normal memory and cacheable. But when I try to read thar area...