• Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
  • Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
  • Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?
    As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode. I'm curious about the handling of Interrupt Service Routine during the lock-step mode. ...
  • Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?
    As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode. I'm curious about the handling of Interrupt Service Routine during the lock-step mode. ...
  • how can the gic600AE set interrupt router relationship by affility when the corresponded cores in DSU(such as A78AE) under lock step mode
    I was building an interrupt system with GIC600AE for A78AE cpu, and i met a question that if i set the A78 cores in locked step mode, its affility attribute would changed, for example ,a cluster with...