MMU - Permission Fault with EL1 access

Hello everyone, I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal). I've successfully...
MMU - Permission Fault with EL1 access

Hello everyone, I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal). I've successfully...
MMU execution permission fault in kernel space

Hi, my 4k sectioned ttbr1 setup is write and readable, so that I can load executable code (the kernel there), when I want to branch there and hand start the kernel I'm receiving a permission fault....
Where is 'The level associated with MMU faults' referenced multiple times in Exception Register documentation

Hello, I am dealing with a "Permission fault, level 3" in my program and wanted to read the documentation to get to the root of the exception. In the Aarch64 Registers for Armv8-A the following ist...
Where is 'The level associated with MMU faults' referenced multiple times in Exception Register documentation

Hello, I am dealing with a "Permission fault, level 3" in my program and wanted to read the documentation to get to the root of the exception. In the Aarch64 Registers for Armv8-A the following ist...