How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?

Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...
How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?

Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...
AXI Read Transaction Dependencies

What if RVALID is asserted before the ARVALID and ARREADY, and also RREADY has been already asserted?
AXI Read Transaction Dependencies

What if RVALID is asserted before the ARVALID and ARREADY, and also RREADY has been already asserted?
In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal

Hi, I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second...