• Basic cortex A9 architecture question (memory area division)
    Hello all, I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip . The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has...
  • Basic cortex A9 architecture question (memory area division)
    Hello all, I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip . The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has...
  • Question about LPAE(Large Physical Address Extensions) for ARMv7
    I read the ARMv7 architecture reference manuals. The spec. says LPAE allows 32-bits VA to be translated into 40-bits PA. The 40-bits PA means the width of address bus is 40-bits or greater than 40 bits...
  • Question about LPAE(Large Physical Address Extensions) for ARMv7
    I read the ARMv7 architecture reference manuals. The spec. says LPAE allows 32-bits VA to be translated into 40-bits PA. The 40-bits PA means the width of address bus is 40-bits or greater than 40 bits...
  • memory address for a variable
    How is it possible to tell a variable / or struct array their specific memory address? e.g. I store the whole c-file in the internal ram (linker-script) and only this one variable I want to store...