• Protection Control Bits of DMA Controller
    Can someone shed some light on how bufferable and cacheable features work in ARM9 DMA controller? An example would be much appreciated. What are the differences between them?
  • Protection Control Bits of DMA Controller
    Can someone shed some light on how bufferable and cacheable features work in ARM9 DMA controller? An example would be much appreciated. What are the differences between them?
  • About AHB5 protection control signals
    In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some...
  • About AHB5 protection control signals
    In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some...
  • Read Protection Status and Set Protection Commands
    I saw a reference to the Read Protection Status and Set Protection commands in Application Note AN1496 from ST. These commands relate to reading and setting the internal flash proteciton register. However...