making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

hi : I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*). however, I can not find any clue about flushing L2 cache to DRAM(if without L3). and I saw some points that...
is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

hi : I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*). however, I can not find any clue about flushing L2 cache to DRAM(if without L3). and I saw some points that...
Invalid entry - mmu page tables

Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...