Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
Freescale K22 Cortex-M4 cpu : why Core Lock Up state occurs ???

I am using Cortex m4 processor from freescale K22, In boot loader i download my firmware and after that I do following steps to soft restart // Disable - WatchDog and disbled IRQ. WDT_DISABLE();...
Freescale K22 Cortex-M4 cpu : why Core Lock Up state occurs ???

I am using Cortex m4 processor from freescale K22, In boot loader i download my firmware and after that I do following steps to soft restart // Disable - WatchDog and disbled IRQ. WDT_DISABLE();...
How to realise a dual-core "LOCK-STEP" Cortex-M7 at the integration level？

Is here any detail information or integration guide？ how to realise the compare logic ，only to compare the CM7 core interface？