Non-Cacheable memory and DMA on armv7a

Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
Non-Cacheable memory and DMA on armv7a

Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
What's the relationship between exclusive access and memory cacheable in Cortex A53?

Hello community and experts, I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'. When I config memory to Normal type+cacheable, 'ldaxr' can execute...
What's the relationship between exclusive access and memory cacheable in Cortex A53?

Hello community and experts, I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'. When I config memory to Normal type+cacheable, 'ldaxr' can execute...
ARM Cortex-A9 | Non-cacheable memory range

Note: This was originally posted on 23rd May 2013 at http://forums.arm.com Hi all, I am designing an application on xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using...