Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions. The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr} The ICI bits...
Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions. The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr} The ICI bits...
AXI transaction when ldm/stm instruction used on cortex-a9

Note: This was originally posted on 15th September 2011 at http://forums.arm.com HI, ARM experts I used ldm/stm instruction to copy(read-write) memory with caches disabled. The code is listed as: int...
AXI transaction when ldm/stm instruction used on cortex-a9

Note: This was originally posted on 15th September 2011 at http://forums.arm.com HI, ARM experts I used ldm/stm instruction to copy(read-write) memory with caches disabled. The code is listed as: int...
ldm/stm with not aligned 4byte

Hi experts! I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes. I know their input address should be aligned by 4 bytes. but is there any solution to use ldr/str or ldm/stm though src...