What happens to the Instructions already in pipeline when interrupt occurs ?

Hello Community, Recently I was going through some code and has this doubt. My Pseudocode ============ CPSID I - Disable interrupts Do critical work CPSIE I - Enable interrupts Do non critical...
What happens to the Instructions already in pipeline when interrupt occurs ?

Hello Community, Recently I was going through some code and has this doubt. My Pseudocode ============ CPSID I - Disable interrupts Do critical work CPSIE I - Enable interrupts Do non critical...
lpc 2138 U0IER disabled but interrupt happens - emulator

I see the strange behaviour in the emulator: I have installed U0IRQ in my vic and enabled it. Also, i have disabled all types of interrupts in U0IER. But after I send some data to serial with this...
lpc 2138 U0IER disabled but interrupt happens - emulator

I see the strange behaviour in the emulator: I have installed U0IRQ in my vic and enabled it. Also, i have disabled all types of interrupts in U0IER. But after I send some data to serial with this...
Cortex-M4 interrupt occures right after it's disabled

Hi! I use STM32F417 with cortex-M4 core in my project. I found that a timer interrupt occures just after 2 instruction after disabled through peripherial register. How iis it possible? Assembler code...