• Why Cortex-R5 Bus-ECC documentation different from Cortex-R7
    Hello Support, In the Cortex-R5 TRM [Section 9.1.1 -- Bus ECC -- Chapter is  Level Two Interface] I see the following statement: " It is possible that fatal, that is double-bit, ECC errors might cause...
  • Why Cortex-R5 Bus-ECC documentation different from Cortex-R7
    Hello Support, In the Cortex-R5 TRM [Section 9.1.1 -- Bus ECC -- Chapter is  Level Two Interface] I see the following statement: " It is possible that fatal, that is double-bit, ECC errors might cause...
  • A contraction between Keil and ST documentation
    Hello, Maybe somebody from Keil can explain this; I still haven't tried it on the device itself, but it would be refreshing to understand the actual requirements. Trying to run a STR9 at 96 MHz, I...
  • A contraction between Keil and ST documentation
    Hello, Maybe somebody from Keil can explain this; I still haven't tried it on the device itself, but it would be refreshing to understand the actual requirements. Trying to run a STR9 at 96 MHz, I...
  • Real differences between Cortex-R and M
    Hello, I'm doing some research about hard real-time systems. I would like to know what are the differences that make a Cortex-R more suitable for hard real-time tasks. I'm asking here because I have...