Cache cleaning and invalidating in ARM Cortex-A

Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two...
Cache cleaning and invalidating in ARM Cortex-A

Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two...
clean and invalidate cache behavior before same address read

I am running on cortex-A17. when following, step1: STR R0, [R1] ; [R1] is cacheable step2: DCCIMVAC ; clean and invalidate cache step3: LDR R0, [R1] ; memory read Does step3 access...
clean and invalidate cache behavior before same address read

I am running on cortex-A17. when following, step1: STR R0, [R1] ; [R1] is cacheable step2: DCCIMVAC ; clean and invalidate cache step3: LDR R0, [R1] ; memory read Does step3 access...
I want to know how to invalidate or clean to cache only used secure-world

Hello experts. I making a security operating system using trustzone using ARMv8 big-little core. I face some probleam of cache clean or invalidate. I want to cache flush to used only secure-world memory...