Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM

Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...
Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM

Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...
Non-Cacheable memory and DMA on armv7a

Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
Non-Cacheable memory and DMA on armv7a

Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
M7 atomic operation faults on non cacheable memory

I'm trying to make one region of SRAM non cacheable for DMA buffers. But what I have found is that when I do that, the first atomic operation bus faults (eg RTOS mutex). Here's an example where I made...