stage2 translation fault ,post-indexing instructions invalid when virtualizing , the ISV bit is 0.

We use a hypervisor(ARM64), if a guest accessed memory outside of a memslot (handle mmio)using any of the load/store instructions in the architecture which doesn't supply decoding information in the ESR_EL2...
page table Cachability bit effect!

Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
page table Cachability bit effect!

Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
MMU page table linking with relative addressing

To my understanding the page tables entries that point to the next page table need to be absolute addresses, so from 0x0. Now I would like to generate my page tables before runtime and cannot know the...
use of bit as array index fails? (if bit is set)

Hi, I suspect I have hit upon a bug in C51 V6. When a bit variable is used as an index into array of int or long int, it fails. Actually, it fails only if the bit is 1; otherwise it works ok. I...