• How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?
    Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is:...
  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?
    Hello, I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is:...
  • How to map tag RAM banks to data cache lines in Cortex-R5?
    Hi, We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data...
  • How to map tag RAM banks to data cache lines in Cortex-R5?
    Hi, We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data...
  • Store operations where the cache line is already cached (ACE protocol)
    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under " Store operations where the cache line is already cache d" as : The initiating master component...