How stable is C/C++ structure padding under the AAPCS (ARM ABI)?

This question was initially posted on stackoverflow , but I have so far only received non-ARM specific information , and ARM-specific information is what I am looking for. The rest of the text below is...
How stable is C/C++ structure padding under the AAPCS (ARM ABI)?

This question was initially posted on stackoverflow , but I have so far only received non-ARM specific information , and ARM-specific information is what I am looking for. The rest of the text below is...
CortexM4 -mfloat-abi=hard, linker error

I am trying to build baremetal binary for cortexm4 using fpu=fpv4-sp-d16 and float-abi=hard options. While building with float-abi=soft works fine, as soon as I switch to hardware fpu, i get linker...
Regarding Linux aarch64 calling conventions (ABI)

In the documenttion I've seen, it appears that the first 8 registers x0-x7 are for parameter passing and don't need to be saved. But this is always vaguely defined so I need to ask: If function A...
CortexM4 -mfloat-abi=hard, linker error

I am trying to build baremetal binary for cortexm4 using fpu=fpv4-sp-d16 and float-abi=hard options. While building with float-abi=soft works fine, as soon as I switch to hardware fpu, i get linker...