PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
Data synchronization Barrier and cache.

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
Data synchronization Barrier and cache.

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8?

Hi Fellows, I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction...