TLB stage2 translation

hi,all.I am working to implement 2 level TLB ,and i notice that the TLB have stage 2 translation when at no secure EL0 and EL1 translation regime。but i doubt if i also need to implement stage2 in 2 level...
TLB stage2 translation

hi,all.I am working to implement 2 level TLB ,and i notice that the TLB have stage 2 translation when at no secure EL0 and EL1 translation regime。but i doubt if i also need to implement stage2 in 2 level...
Why does Arm still support short descriptors?

What I'm asking is ARM Architecture Reference Manual for ARMv8-A says in AArch32 there are two translation table formats: Short descriptors: 32 bit Long descriptors: 64 bit On page G4-4726...
Why does Arm still support short descriptors?

What I'm asking is ARM Architecture Reference Manual for ARMv8-A says in AArch32 there are two translation table formats: Short descriptors: 32 bit Long descriptors: 64 bit On page G4-4726...
stage2 translation fault ,post-indexing instructions invalid when virtualizing , the ISV bit is 0.

We use a hypervisor(ARM64), if a guest accessed memory outside of a memslot (handle mmio)using any of the load/store instructions in the architecture which doesn't supply decoding information in the ESR_EL2...