How do the TLB maintenance instructions affect other offline CPU cores disabled by CPU Hotplug in the kernel

Hi, I'm a beginner in ARM architecture. 1) A re some TLBI instructions that can clean TLB entry for the Outer Shareable domain valid for other CPU cores that are offline? For example, if I make a...
what is the Instruction L1 TLB and L2 TLB size?

if L1 TLB size = 32entry*64Byte = 2048 = 2k? L1 TLB cache line is 64Byte, becuse the entry size is 64 byte.I don't know if my understanding is correct.
what is the Instruction L1 TLB and L2 TLB size?

if L1 TLB size = 32entry*64Byte = 2048 = 2k? L1 TLB cache line is 64Byte, becuse the entry size is 64 byte.I don't know if my understanding is correct.
TLB translate

i want to know why the application point to flash, what is the scenario？ why does not OS point to RAM
TLB translate

i want to know why the application point to flash, what is the scenario？ why does not OS point to RAM