Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...
Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...
Dual A53 cluster, MMU configuration

Hello, we have a A53 cluster with two cores, core 0 and core 1. is there any possibility that the MMU configuration of core 1 is only done by core 0?since on core 1 a non secure application is running...
how to understand ARMv8 exception level1 secure/non-secure MMU?

Hi Experts , ARMv8 MMU TTBRn_ELx registers are banked by exception level. In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1 and Non-secure...
how to understand ARMv8 exception level1 secure/non-secure MMU?

Hi Experts , ARMv8 MMU TTBRn_ELx registers are banked by exception level. In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1 and Non-secure...