Disabling L2 cache for CPU1 (Zynq-7000)

Hello people, we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one...
Disabling L2 cache for CPU1 (Zynq-7000)

Hello people, we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one...
Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
Re-build tensorflow lite model in cmsis-nn

Hi, Is it possible to rebuild a tensorflow lite model with cmsis-nn to run on a MCU with a Cortex-M? We have followed the guide posted on arm:s website for converting neural networks for ARM Cortex...