Deadlock accross multiple interconnects

Note: This was originally posted on 5th January 2011 at http://forums.arm.com For single AXI matrix, the interconnect can ensure that deadlock cannot occur via CDAS , however, could you please give me...
Address decoding in AXI4 interconnect

Hi, anybody explain how data is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
Cortex-A53 backward compatible with AXI-4 interconnect

Hi, The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if...
How to learn ARM

Hi everyone!! I am looking to work on some projects using ARM. I have completed a basic course on ARM M3/M4 (UT Austin 6.01x by Jon Valvano and Ramesh Yerraballi) online. Now, I want to learn advanced...
Learning lpcxpresso

Hi friends I am new to lpcxpresso. I have lpc1769 kit and I am thinking of buying books on arm cortex m3 to get familiar with it. Is it worth? If then how much is it helpful? Additionally I was thinking...