Deadlock accross multiple interconnects

Note: This was originally posted on 5th January 2011 at http://forums.arm.com For single AXI matrix, the interconnect can ensure that deadlock cannot occur via CDAS , however, could you please give me...
Address decoding in AXI4 interconnect

Hi, anybody explain how data is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
Cortex-A53 backward compatible with AXI-4 interconnect

Hi, The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if...
Difference between PL080 and PL330

Note: This was originally posted on 4th April 2012 at http://forums.arm.com What is the difference between PL080 and PL330 as both are DMAC controller.
Hello, my question is about watchpoint.

When I set a on-chip breakpoint with MMU enabled, virtual address is 0xcc000000 ( real physical address is 0xbb000000)for example. Once the MMU map changed, when the breakpoint would be hit, new virtual...