Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
Arm big.LITTLE, migration decision

Hi everybody, I'm doing a presentation about ARM big.LITTLE Technology. What is the tracked load metric that is used to decide whether and when to allocate a thread to a big or LITTLE core?
General Feature of Cortex processors on cache coherency

Hi Experts, Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ? I found some features like CCI module available to provide this feature in multi...
io coherency and shareability

Hi, I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a...
Is Cache Stashing introduced in DynamIQ similar to IO coherency?

IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to...