Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
General Feature of Cortex processors on cache coherency

Hi Experts, Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ? I found some features like CCI module available to provide this feature in multi...
Is Cache Stashing introduced in DynamIQ similar to IO coherency?

IO coherency also allows device to access coherent memory space. The only difference I noticed is that cache stashing connects device directly with cluster, however, IO coherency transactions need to...
io coherency and shareability

Hi, I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a...
Multi core L1 cache coherent

Dear experts, I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation. Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached)...