MCU Development - Endianness - Big Endian

For those of ARM's customers, who design microcontrollers, I would like to recommend a Big Endian implementation (or at least an option to select Big Endian). This is due to that I have designs that need...
The number of big cores in Dynamiq cluster?

Is four the maximum number of big cores in a Dynamiq cluster? why is it? memory bandwidth? or soc routing concerns? Is o ne big cluster (4 big + 4 little) feasible in terms of routing? Is it preferable...
Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

Hi, As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian...
Running an app on big and LITTLE cores simultaneously?

Hello everyone, I am running an application on Renesas R-Car H3 board. It has Cortex A57 and A53 CPUs. I am getting limited performance from running application on all 4 cores of the A57. I wanted...
Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

This question was raised in the ‘ Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post .