TRACE Signal usage in AXI5, ACE5, ACE5-lite

Is there any detail explanations about what should be the usage of the "TRACE" signal in all channels of AXI, ACE, ACE-lite ? In CCI-550, I think one of its usage is : When we read a data , if the data...
Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior

Hi, The AMBA5 spec for ACE5 shows some new signals versus ACE4 : VAWQOSACCEPT VARQOSACCEPT AWAKEUP ACWAKEUP SYSCOREQ SYSCOACK How are these used in an SOC system ? For example, I think...
AXI5 : Untranslated Transactions property for A*MMU* signals and similarly for AXI5-Lite for AWSTASH*

Hi, I'm trying to add some checks for AXI5 / AXI5 -Lite protocol. When Untranslated Transaction is TRUE, do all of the signals A[R/W]MMUSECSID A[R/W]MMUSID A[R/W]MMUSSIDV A[R/W]MMUSSID ...
CHI/ ACE-Lite Interface

I have a custom accelerator to be integrated with Corelink CMN-600. The CMN-600 has a CHI/ ACE-Lite Interface. How can I add a CHI/ ACE-Lite Interface to my custom accelerator? Is there a tool which can...
AXI-lite tlast signal missing and tready behavioral

Dear Forum, Can someone please clarify my 2 questions: a) Why in AXI lite protocol there is no tlast port? Mainly AXI lite consists of AXI-stream protocols, but there is no tlast port...