AMBA AHB Lite addressable space for byte size transfer

Hi, It looks like when using a transfer size of one Byte, the position of this data on the 32-Bit bus must be set via ADDRESS[1:0]. This means that for a Byte transfer, the addressable space is reduced...
Endian about AHB-Lite and AHB5 Specification

Hello to all, I have a question about AMBA3 AHB-Lite and AHB5 Specification: In AMBA3 AHB-Lite Specification, " Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant...
Question about AHB-Lite interconnection

Hello to all AHB experts, I have some question about AHB-Lite interconnection. If I want to build 2 masters share 1 slave systems. I add a arbiter in the interconnect circuit, so that only one master...
AHB Lite Response

Hi All, I have doubt in ahb_lite hresp signaling when the address phase is extending. In the following diagram transfer address c is extending because of data phase of B. In 3rd clk cycle address...
AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...