AXI

Why burst must not cross 4kb in AXI ?
AXI transfer

Consider Data interface is 64 bit. It is Write transfer. AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios. Scenario...
AXI WVALID before AWVALID

what happen if WVALID asserted before AWVALID ??
Write Data Interleaving - AXI

Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hello, Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec...
AXI WRITE DATA CHANNEL

Hi All, I am doing single write operation to AXI slave from avalon BFM. The data and address signals are reached into the axi slave.But if i am try to read back the data which i have written in the...