Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
single burst in ahb lite

HI I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not. If i am using a write based read ,The write is not complete due to wait at the time ,At...
AHB Busy states...

Note: This was originally posted on 24th November 2008 at http://forums.arm.com Hello guys.... If master is doing transfer of fixed length burst and last address is driven on bus... Can master drive htrans...
quiery about AHB burst mode

Note: This was originally posted on 19th November 2008 at http://forums.arm.com hi, in the AHB burst mode is it the Master that drives consecutive address to slave, or is it that the master only sends...
In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

Hi, In AMBA AHB:- For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response. q) For two clock cycle ERROR response, is it mandatory of hgrant...