In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

Hi, In AMBA AHB:- For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response. q) For two clock cycle ERROR response, is it mandatory of hgrant...
AHB Slave HREADY

Hello I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs. My question is Is there any specific condition for slave when it gives HREADY low? I am confused with HREADY...
In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

I am a Digital Verification Design Engineer. Currently, I am in the process of developing an UVM Test Bench for AHB 2.0. I have following questions. 1) From AHB Master side, Can BUSY cycles be inserted...
AHB WRAP address boundaries

Note: This was originally posted on 18th June 2008 at http://forums.arm.com AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same...
Relation between Hsel and Hready in AMBA AHB

Hi, In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase...