AHB HREADY low not after address phase

What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles. Thanks
In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

I am a Digital Verification Design Engineer. Currently, I am in the process of developing an UVM Test Bench for AHB 2.0. I have following questions. 1) From AHB Master side, Can BUSY cycles be inserted...
AHB split retry response

Note: This was originally posted on 9th December 2008 at http://forums.arm.com IN AMBA AHB , there are split and retry response. These are 2 cycle responses. whole SPLIT sequence is given in the spec...
AHB master continues transfer after error response

Hi Everyone, Consider an AHB transaction in which the AHB slave signals an error response, and the AHB master decides to continue the transfer with the present slave. Following are three waveforms that...
AMBA AHB

1)what are the different generations in AMBA AHB?