MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

Hi, Facing the issue: "MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave" Here is the Inputs: We are using the custom SOC, in which we are testing...
AHB slave

1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high? 2.) Is there any possibilities that if write transaction is in progress and if burst is not completed...
AHB lite single master single slave

I have completed the material provided by arm, can i plz have a simple code of single master and single slave in ahb_lite protocol for better understanding?
AHB Slave HREADY

Hello I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs. My question is Is there any specific condition for slave when it gives HREADY low? I am confused with HREADY...
Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ?

PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH. APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should...