Lock Signal for AXI Slave

According to what I read in AXi spec sheet, AxLOCK signals are used by the Masters for a locked access to a slave and it's the arbiter/interconnect which takes care of the AxLOCK signal. Am I right when...
Three question on AXI transfers, related to disjoint byte access in a single 4 byte word, single transfer.

I have three question on AXI transfers, and these all relate to a) my understanding of the spec, as all question do, and b) a single write transfer to a single 32-bit aligned address. I would like to...
AXI3 locked access

I want to know what happens in these scenarios : 1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1? 2) Assume M1...
Sampling on positive edge of clock of slave in AXI3

How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
AHB slave

1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high? 2.) Is there any possibilities that if write transaction is in progress and if burst is not completed...