• AHB Slave HREADY
    Hello I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs. My question is Is there any specific condition for slave when it gives HREADY low? I am confused with HREADY...
  • AHB Busy states...
    Note: This was originally posted on 24th November 2008 at http://forums.arm.com Hello guys.... If master is doing transfer of fixed length burst and last address is driven on bus... Can master drive htrans...
  • Relation between Hsel and Hready in AMBA AHB
    Hi, In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase...
  • AHB HREADY low not after address phase
    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles. Thanks
  • HREADY signal and single transfer in ahb lite
    HI... A) 1). I am now using a continuously 10 transfer of the SINGLE BURST write based read transfer. In spec says the default ready signal is HIGH. 2).First thing i complete the first transfer...