AXI read response in error case

Hi, In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat. Now my question here...
axi read transfers

what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?
AXI read transfer

If the slave is not able to process read request from master, which response is expected from slave?
AMBA AXI Write response

I am just going through the specs of AMBA AXI. I've few questions.It will be great if anybody clarify 1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response...
AXI transfer

Consider Data interface is 64 bit. It is Write transfer. AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios. Scenario...