AXI4

In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this? What is the meaning of bandwidth in this context? What are the values of bandwidth...
AXI4 - read data interleaving

Hi Folks, We need a clarification on Read Data Interleaving on AXI4 Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving: Multiple Read commands can be executed...
Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers.

There seems to be a slight inconsistency in the following paragraph about INCR burst transfers on page A3-50: In an incrementing burst, the address fo r each transfer in the burst is an increment...
Is there a limit for AXI4 outstanding transaction?

Hi all! I'm working on an avalon to axi4 master writing bridge module. In many cases,I need to assert a large number of awvalid continually for writing efficiency(for instance, a frame of 4K video data...
Removal of WID's in AMBA AXI4

Hi , What is the purpose of removing ID's (WID) in AXI4 ? If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please...