Question related to Phases in APB

Hi All, In APB, There are two phases. SETUP and ACCESS. The ACCESS phase is indicated by assertion of PENABLE signal. My question is why we require this phases ?? The signal PENABLE can be driven...
Is M3 DesignStart similar to M7 Design Kit? (I don't yet have M7 Design Kit)

Just starting... Is it reasonable to work through M3 DesignStart as an intro to M7 Design Kit? (I do not yet have access to M7 Design Kit, but want to get a head start on my ARM project) I'm hoping that...
AHB response relation with data

Note: This was originally posted on 30th September 2008 at http://forums.arm.com Hi, I have an issue regarding AHB responses relation with data in case of AHB write transfers . As we know that the address...
AHB-Lite IDLE and hready related queries

Hi, Can someone clarify below queries I have wrt AHB-Lite, Is there any relation between HTRANS=IDLE and hready ? Like, Whenever IDLE comes hready is de-asserted (or) Whenever hready is de...
Is there relation between the de-assertion of BVALID and BREADY signals ?

Hi, I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one...