AXI channel handshake process

for a VALID before READY handshake process in AXI channel, AXI reference manual states that "A source is not permitted to wait until READY is asserted before asserting VALID" Guide me with this statement...
AXI WRITE DATA CHANNEL

Hi All, I am doing single write operation to AXI slave from avalon BFM. The data and address signals are reached into the axi slave.But if i am try to read back the data which i have written in the...
AXI data channel

After the data transfers in a burst are over on the data channel, let us say the response gets delayed on the write response channel. During this waiting for response interval, are the data transfers...
AXI handshake between AW/AR-READY and B/R-RESP

In AXI Write how the handshake between AW channel and B channel is taken care. Standard says that "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID" Does that...
AXI4-Relationships between the channels

A statement in AXI4 specification says that " the write data can appear at an interface before the write address that relates to it. This can occur when the write address channel contains more register...