• AXI4:- Unaligned transfer
    While doing an unaligned transfer of 32-bit data on 64-bit data, using 0x001 address, lower address lines used to indicate an unaligned data transfer but what if this lower address line data also needs...
  • Write strobe for AXI4 lite
    what are the possible values of strobe for a half word transfer in AXI4 lite? Are these following values on WSTRB valid ? -1001 -0101 -1010
  • Axi4 Write Transaction
    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
  • AXI4
    AXI4 specification says that AXI is a point to point interface. Can you explain this statement meaning and it's significance?
  • AXI4
    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this? What is the meaning of bandwidth in this context? What are the values of bandwidth...