AXI narrow read with unaligned address

Hi, I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario: - 32 bit data bus - address x0001 - length 0 (1 beat...
burst-based transactions on AXI

Hi, I'm confusing with burst transaction in AXI. there is one key feature in AXI spec.... > "burst-based transactions with only start address issued" How can we understand this point? ...
[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?

Hello, A couple of further details on the question. Let's assume that I have a 64-bit data bus and a 32-bit address bus. A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0]...
Lock Signal for AXI Slave

According to what I read in AXi spec sheet, AxLOCK signals are used by the Masters for a locked access to a slave and it's the arbiter/interconnect which takes care of the AxLOCK signal. Am I right when...
AXI Burst Size meaning

Dear Community, I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction. a) I cannot clearly understand the meaning of Burst...