AHB_LITE Extended address phase

Hi All , The following figure shows the INCR4 burst transaction. Here the address increment is happening in each clk cycle As per AHB protocol Single outstanding address is allowed. What are the...
State Machine for AHB-Lite Protocol

This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and...
Error scenario in AHB protocol

Hi, I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB? 1.I can think of invalid address as the only case. Is there any other scenario...
Question about AHB-Lite interconnection

Hello to all AHB experts, I have some question about AHB-Lite interconnection. If I want to build 2 masters share 1 slave systems. I add a arbiter in the interconnect circuit, so that only one master...
AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...