outstanding transaction in AXI4 protocol

Hi, I am using single AXI4 master to issue outstanding transaction with two AXI4 slave. Can a single master issue outstanding transaction with more than one slave? i.e. can master transfer data...
Is there a limit for AXI4 outstanding transaction?

Hi all! I'm working on an avalon to axi4 master writing bridge module. In many cases,I need to assert a large number of awvalid continually for writing efficiency(for instance, a frame of 4K video data...
AXI4 Burst Transactions

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction. Eg. Burst length- Two , Burst size 16 bytes. Please give me answers...
Axi4 Write Transaction

I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
AXI4 transaction attributes

AXI specifications states for AxCACHE[1] bit is that: When this bit is asserted: For writes this means that a number of different writes can be merged together. For reads this means that the contents...