• Wrap address usage?
    Note: This was originally posted on 18th October 2008 at http://forums.arm.com Hello guys.. I am working on AMBA AHB... and came across the wrap address term... Can you tell me that which kind of application...
  • ARM Cortex ICode, DCode, System buses
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have...
  • Assertion for Multiple Transfer on APB Bus
    Hi, Can you please help me in writing assertions to take care on multiple transfer in APB bus? Thanks, Rakesh
  • AMBA
    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low...
  • In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?
    Hi, In AMBA AHB:-      For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.    q)  For two clock cycle ERROR response, is it mandatory of hgrant...