AHB response relation with data

Note: This was originally posted on 30th September 2008 at http://forums.arm.com Hi, I have an issue regarding AHB responses relation with data in case of AHB write transfers . As we know that the address...
AMBA AHB HSPLITx signal.....

Note: This was originally posted on 30th September 2008 at http://forums.arm.com Hi guys... I am trouble again..... My question is : If slave 0 gives split error to two masters say master 0 and master...
AHB Bufferable/Non-bufferable write

Note: This was originally posted on 12th September 2008 at http://forums.arm.com Hi, Please clarify the following issue related to AHB write: If HPROT[2] = 1, AHB write is bufferable and we need to provide...
In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

I am a Digital Verification Design Engineer. Currently, I am in the process of developing an UVM Test Bench for AHB 2.0. I have following questions. 1) From AHB Master side, Can BUSY cycles be inserted...
single burst in ahb lite

HI I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not. If i am using a write based read ,The write is not complete due to wait at the time ,At...