AHB Busy states...

Note: This was originally posted on 24th November 2008 at http://forums.arm.com Hello guys.... If master is doing transfer of fixed length burst and last address is driven on bus... Can master drive htrans...
Data during AHB Busy state

Hi everyone, I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave: TIME: T1 T2 T3 T4...
In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

I am a Digital Verification Design Engineer. Currently, I am in the process of developing an UVM Test Bench for AHB 2.0. I have following questions. 1) From AHB Master side, Can BUSY cycles be inserted...
BUSY transfer just before the last transfer in a burst by a AHB Master.

Normally the AHB arbiter will only grant a different bus master when a burst is completing. Suppose for a INCR4 burst it can change the grant once it samples the 3rd address with SEQ transfer. As depicted...
single burst in ahb lite

HI I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not. If i am using a write based read ,The write is not complete due to wait at the time ,At...