GICv2 How to resolve Multiple Interrupt appearing on a CPU

Hi All, I am facing issue where, in the event of multiple interrupts on GIC in close vicinity, I am unable to decide on which interrupt has been asserted, to service them properly. Details:- This...
To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured?

I'm just trying to generate an FIQ from GIC .All the interrupts are by default grouped to Group0 and apart from setting FIQEn trying to understand what else needs to be configured..
GICv2 deactivation feature.

Hello all, There is one thing which is unclear for me in GICv2. GICv3 spec. explicitly says "SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a...
Finding design errors before it’s too late

What are Design Reviews? Design Reviews are a service offered by Arm whereby expert engineers visit our partners to perform a detailed review of a particular stage of the design cycle. Based on that...
[ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface!

Hi all, I am investigating the GIC Stream protocol and having a confusing issue as the title. The figure below shows the case that an interrupt is retrieved from CPU interface. As explained in...