How do I add AHB interface to a processor with Load Store Architecture?

I need to add/encorporate AHB interface to a processor with Load/Store Architecture, which has already been designed. But the processor has only data bus for both input and output. Is it possible to still...
single burst in ahb lite

HI I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not. If i am using a write based read ,The write is not complete due to wait at the time ,At...
What purpose do wrapping BURST transfers serve?

I've understood how it works and what happens in it, but what is the use of having a wrapping bursts? What are some scenarios where it provides an edge?
Does AHB-Lite Protocol require the master processor to be pipelined?

The transfers in AHB protocols occur in two phases - address phase and data phase. Does this mean that the processor (Master) must have pipelined architecture?
AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...